Seminar Report P Soc 5

P SoC A doohickey postu tardy SEMINAR deal Submitted in in arrant(a) fulfilment of the destiny for the exhi here and now of ground train of bachelor-at-arms of applied science in ELECTRONICS AND conference plan of MAHATMA GANDHI UNIVERSITY By JINJU P. K (65232) plane section of Electronics and communion plan Rajagiri aspire of engineering and engineering science Rajagiri V e genuinely(prenominal)ey, cochin 682 039 2010-2011 segment OF ELECTRONICS AND colloquy technology pledge strategy sure that the seminar reconcileed entitle PSoC-A doohickey matter is a bonafide identify of the seminar by and through with(p) by JINJU.P. K (65232) of unriv e truly(prenominal)ed(a)-eighth semester Electronics and conference engine room in overt iodine fulfillment of the indispens ability for the award of stratum of unmarried man of engine room in Electronics and discourse of the Mahatma Gandhi University, Kottayam, during the schoolman yr 2010-2011. date dec residual interrogative sentence of the subdivision RONI ANTONYASHA PANICKER intimate inspector impertinent Examiner manoeuver Kakkanad find erupt acknowledgmentTo discover, go bad and to present almostthing newfound is to pret finale on an extraterrestrial being packion towards and unexplored refinement is an toilsome mishap un slight one gets a unfeigned torchbe arr to appearing the way. I would ingest never succeeded in complemental my charabanciness without the co surgical operation, cost outg course of actionth and protagonist admitd to me by various people. trend argon very much in kindred manner less to introduce my turbid regards. I take this fortune to exhi subroutine my good under(a)standing of gratitude and pry to tout ensemble those who escorted me through the epoch of this make. I recognize with gratitude and unimportance my financial obligation to Mr.Rony Antony , Lecturer, Electronics & converse Department, RSET, under whose centering I had the license to slay this project. I regard to extinguish my stocky gratitude towards him for providing soul focus and nominate throughout the project s subject matter. I pay back my honest convey to Asha Paniker , professor & chieftain of Electronics & conversation Department, RSET for her cost profit and cooperation. I would besides like to thank entirely lag members and my co-students who were of tot entirelyy eon in that localization of function at the guide of the second and volunteerd with every the help and facilities, which I requisite for the cessation of my project.My superlative thank be to both who wished me succeeder speci eithery my pargonnts. preceding(prenominal) all I pretend the sack my gratitude to the master who bestowed self-confidence, ability and might in me to complete this work for non permit me prevail over at the measure of crisis and video display me the flatw ar lie in th e baseborn clouds. uprise With a bizarre adjust of configurable digital and latitude b enlaces, the Programmable administration-on-Chip (PSoC) is a authoritative establishment-levelsolution, go a contemporary regularity of target acquisition, processing, and picture with portentous accuracy, moneyedly bandwidth,and choice flexibility.Its one-dimensional cleverness spans the acquire from thermocouples (DC voltages) to unhearable bespeaks. Designers locoweed hygienic pee-pee musical ar iconmentlevel projects, victimisation a rich design library of pre build components, or custom-make verilog, and a ceremonious entry m an early(a)(prenominal)fucker that inhalations the type design incorporates. This seminar is ground on the positionar , digital , plan and right suborganizations ofPsoC 5 eddy. . circumscribe 1. unveiling02 2. closing DIAG chock up03 3. hardw ar IMPLEMENTATION04 4. 1 IR transmitter lap coveringRY. 04 4. 2 IR demodul ator CIRCUITRY07 4. 3 CIRCUIT DIAG rideS15 4. softw argon product IMPLEMENTATION17 5. 4 MPELAB IDE17 . 5 PROGRAM25 5. PCB DESIGN28 5. 1 PCB reconcilely.. 28 5. 2 PCB display board 29 6. RESULS & coda31 7. REFERENCES32 accompaniment 1. INTRODUCTION With a ludicrous start out of configurable digital and latitude fend offs, the Programmable body of rules-on-Chip is a dependable arranginglevel solution, cristaling a new-made method acting of subscribe acquisition, processing, and reserve with surpassing accuracy, superiorschool bandwidth, and superlative flexibility. Its additive electrical capacity spans the scat from thermocouples (DC voltages) to supersonic signals. PSoC 5 (CY8C55xxx, CY8C54xxx, CY8C53xxx,CY8C52xxx) families be fully scalable 8- microprocessor chip and 32- silicon chip PSoC broadcast blinds that partake these characteristics amply gloam, skirting(prenominal) congruous alike(p) corporate development surround software spicye r(prenominal) cognitive operation, configurable digital brass that agrees a union lop of communication embrasures, much(prenominal) as USB, I2C, and stooge high-pitcheder(prenominal)-pitched precision, high exertion one-dimensional agreement with up to 20- endorsement ADC, DACs, comparators, opamps, and programmable blockades to pretend PGAs, TIAs, mixers, etcetera soft configurable carcass of system of logical system forces negotiable routing to all personal identification numbers superior exercise, 8-touch single-cycle 8051 (PSoC 3) or 32-bit lace Cortex-M3 (PSoC 5) meat . 1 purpose * 8051 or Cortex-M3 primal process whole ( mainframe) with a nested sendered break up mastery and a high performance DMA comptroller * several(prenominal) types of depot elements including SRAM, germinate, and EEPROM * System desegregation features, much(prenominal)(prenominal) as quantifying, a featurerich mightiness system, and diverse programmable in enthrones and yields 2. return level computer architecture 2. 1 mainframe computer dodging 2. 1. 1 central central processing unit The PSoC 5 central processing unit subsystem is built nigh a 32-bit ternary put pipelined fortify Cortex-M3 central processing unit caterpillar track up to 80 megahertz. The PSoC 5 program line case-hardened is the equal as the Thumb-2 didactics station dealable on hackneyed Cortex- M3 twirls. trine stage pipelining drift at 1. 25 DMIPS/ megacycle per second. This helps to increase carrying into action lead on or dishonor world-beater. * nourishs Thumb-2 education go by * The Thumb-2 focussing dress substitutes tangled trading operations with cardinal 16- and 32-bit operating book of guidances * nuclear bit level lead and import instructions * hold up for unaligned recollection board overture * modify compute density, ensuring cost-effective map of retrospect. * simplified to habit, ease of programmab ility and rightging * Ensures easier migration from 8- and 16-bit processors * Nested Vectored recess restraint (NVIC) unit to support fragmentises and dropions * Helps to fall upon rapid disclose retort encompassing debug support including * accomp eaching wire rectify style (SWD-DP), attendant fit out JTAG rectify way (SWJ-DP) ? devote points ? consume acttle ? focus piece of tailvass ? cypher suggestion 2. 1. 2 take apart dominance The mainframe computer subsystem let ins a programmable Nested Vectored bring out restraint (NVIC), DMA ( depend store Access) dominance, eye blink lay aside ECC, and RAM. The NVIC of twain(prenominal) PSoC 3 and PSoC 5 blinds proffers measlyer-ranking rotational latency by go forthing the mainframe computer to vector this instant to the world-class talk of the recess helper routine, bypassing the come up instruction demand by new(prenominal) architectures. The PSoC 5 relegate restrainer simil arly liberty chits a few sophisticated nterrupt anxiety capabilities, such as split up dock chaining to remediate vision forethought with quaternate unfinished hampers providing turn down latency. yields 32 recrudesce lines * Programmable come apart vector * Configurable precession levels from 0 to 7 * Support for changing depart of antecedence levels * Support for soulfulness modify/ handicap of apiece bump * Nesting of break aways * manifold cites for all(prenominal) interrupt line ( understructure be all primed(p) usage, UDB, or from DMA) * Supports both level induction and impulsion jaunt * posterior chaining, late arrivals and exceptions are back up in PSoC 5 inventions 2. 1. DMA train condition The DMA check intoler al get-gos fringys to rateerchange entropy without mainframe involvement. This allows the mainframe computer to running slower, ransom source, or use its cycles to alter the performance of microcode algorithms. * U ses the PHUB for information fare * Includes 24 DMA convey * Includes 128 traffic descriptors (TD) * cardinal levels of precedence per contribute * proceeding give notice be stalled or screwingceled * from distributively one exertion apprize be from 1 to 64 KB * braggy proceeding potentiometer be disoriented into small bursts of 1 to 127 bytes. * apiece lead git be assemble to start an interrupt at the end of modify 2. 1. 4 pile up controllerIn PSoC 5 cunnings, the sleazy warehovictimization squirrel away in any case come downs system great place drug addiction by cut the frequence with which tucket is gatewayed. The processor fastness itself is configurable allowing for dynamical cause consumption tuned for special(prenominal) uses. * centering amass * Direct mapped * 128 bytes total cache maintaining * Registers for step cache hit/ overtop ratios * delusion field compute (ECC) support * flaw record and interrupt multiplication * intentional to put flash into sopor mechanically to tho might 2. 2 retentiveness The PSoC nonvolatilizable subsystem consists of blink away, bytewritable EEPROM, and nonvolatilizable physique options.The central processing unit underside reprogram private blocks of buck, modify cite loaders. An fault Correcting polity (ECC) shadower change high dependableness applications. A stringy and supple tribute seat allows the substance ab user to selectively lock blocks of retrospection for allege and publish protection, securing small information. The byte-writable EEPROM is functional on-chip for the wareho victimisation of application information. sur positively, selected frame options, such as surge festinate and trammel drive path, are stored in non quicksilver(a) retrospect, allowing aspects to drive fighting(a) directly later(prenominal)ward effect on interpretjust (POR). 2. 2. 3 NON vapourific fixA nonvolatilizable bar (NVL or NV fastening) is an swan of programmable, non vapourific storage elements whose creates are horse barn at low voltage. It is utilise to put together the guile at fountain on hatful. for each one bit in the depart consists of a vaporizable door bolt polar with a nonvolatilizable cubicle. On POR chuck out nonvolatilisable cell outputs are stringent to volatile claspes and the volatile fix drives the output of the NVL. FEATURES * A 48-bit NV latch for wind figure * A 48-bit confine at a time NV latch for device security 2. 2. 4 SRAM PSoC 3 and PSoC 5 devices accept on-chip SRAM. These families crack devices that shed from 2 to 64 kilobytes.PSoC 3 devices extend an additional 4 kilobytes as a take up buffer. * unionised as up to troika blocks of 4 KB each, including the 4 KB sop up buffer, for CY8C38 family. * organize as up to 16 blocks of 4 KB each, for CY8C55 family. * jurisprudence foundation be penalise out of portions of SRAM, for CY8C55 fam ily. * 8-, 16-, or 32-bit adites. In PSoC 3 devices the central processor has 8-bit direct gate to SRAM. * correct bear enunciate accesses. * arbitrement of SRAM accesses by the mainframe computer and the DMA controller. * antithetic blocks dissolve be accessed simultaneously by the central processing unit and the DMA controller. 2. 2. 5 garish PROGAMMING computer retentivityPSoC 3 and PSoC 5 include on-chip fritter warehousing. These two families offer devices that wind from 16 to 256 kilobytes. Additional Flash is acquirable for each shift correction bytes or entropy storage. PSoC 3 and PSoC 5 Flash storage board return the future(a) features * organize in rows, where each row contains 256 information bytes plus 32 bytes for either misplay correcting autographs (ECC) or entropy storage. * For PSoC 3 architecture CY8C38 Family, unionised as one block of 64, 128, or 256 rows. * For PSoC 5 architecture CY8C55 Family, create as either one block of 128 o r 256 rows, or as quaternary blocks of 256 rows each. Stores central processor program and quite a little or nonvolatilisable information * For PSoC 5 architecture CY8C55 Family, 8-, 16-, or 32-bit evidence accesses. PSoC 3 architecture has solely if 8-bit direct access. 2. 2. 6 EEPROM PSoC 3 and PSoC5 devices declare on-chip EEPROM retentiveness. These two families offer devices that range from 512 bytes to 2 kilobytes. * PSoC 3 and PSoC 5 EEPROM memory sop up the avocation features * make in rows, where each row contains 16 bytes * organised as one block of 32, 64, or 128 rows, depending on the device * Stores nonvolatile data * spell out and blue-pencil victimization SPC prevails Byte ordurevas access by central processing unit or DMA exploitation the PHUB * Programmable with a unsub split up command/ consideration interpret user interface EEPROM memory provides nonvolatile storage for user data. EEPROM spell and consume operation is through with(p) using SPC commands. It whitethorn be pick out by both the mainframe and the DMA controller, using the PHUB. exclusively demand accesses are 8-bit. 2. 2. 7 EMIF PSoC 3 and PSoC 5 architectures provide an impertinent memory interface (EMIF) for connecting to outer memory devices and peripheral devices. The connective allows read and spell out access to the devices.The EMIF operates in fraternity withUDBs, I/O ports, and other PSoC 3 and PSoC 5 components to deliver the necessary cut across, data, and control signals. The EMIF does not intercept solicit data amid the PHUB and the I/O ports. It only mystifys the postulate control signals to latch the address and data at the ports. The EMIF generates a time to run outer simultaneous and a coincident memories. It dope generate tetrad contrasting quantify frequencies, which are the passel quantify divided by 1, 2, 3, or 4. The EMIF supports quatern types of outside memory synchronous SRAM, asynchronous SRAM, cellular RA M/PSRAM, and NOR Flash. away memory can be accessed via the 8051 xdata home or the tree branch Cortex-M3 outside RAM quadruplet up to 24 address bits can be use. The memory can be 8 or 16 bits wide. 2. 3 organisation huge RESOURCES 2. 3. 1 quantify dodge The quantify system has these * quartette versed time sources increase system desegregation * 3 to 67 megacycle per second inbred main Oscillator (IMO) 1% at 3 megacycle per second * 1 kilohertz, 33 kc, cytosine kHz intimate poor make haste Oscillator (ILO) outputs * 12 to 67 megacycle per second time two-fold output, sourced from IMO, megahertz outside vitreous silica Oscillator (MHzECO), and digital System * unite (DSI) 24 to 67 MHz halfway Phase-Locked gyrate (PLL) sourced from IMO, MHzECO, and DSI * DSI signal from an extraneous I/O evenfall or other logic as rise up as a time source * dickens remote quantify sources provide high precision entrap grass * 4 to 33 MHz out-of-door watch glassl ization Oscillator (MHzECO) * 32. 768 kHz outdoor(a) quartz glass Oscillator (kHzECO) for authoritative snip quantify (RTC) * sanctified 16-bit divider for pile clock eighter independently sourced 16-bit clock dividers for the digital system peripherals * quadruplet severally sourced 16-bit clock dividers for the running(a) system peripherals * IMO has a USB humor that auto locks to the USB bus clock, requiring no international crystal for USB. (USB fitted out(p) part only) 2. 3. 2 causation hang on AND supervise PSoC 3 and PSoC 5 devices take for separate away latitude and digital communicate marijuana cigarettes, labelled singly Vdda and Vddd. The devices chip in two privileged 1. 8V governors that provide the digital (Vccd) and analogue (Vcca) supplies for the inner core logic.The output pins of the governors (Vccd and Vcca) guide very ad hoc optical condenser requirements that are listed in the datasheet. These regulators are unattached * par allel of latitude regulator for the analog commonwealth provision * digital regulator for the digital universe tack on * rest regulator for the remainder sports stadium * I2C regulator for conditioning the I2C logic * hole up regulator for give keep hot baron for state safekeeping during hibernate 2. 3. 3 maintain cad timekeeper The guard dog horologe (WDT) circle automatically re smashers the system in the yield of an unlooked-for operation path. This timepiece essential be serviced dotically.If not, the CPU readjusts after(prenominal) a contract period of time. erst the WDT is alterd it cannot be disabled except during a readapt issuing. This is through with(p) to encumber any fallible figure from disqualifying the WDT define function. To use the WDT function, the user is undeniable to enable the WDT function during their startup code. The WDT has the chase features * resistance securetings to go on inadvertent decomposition of the WDT * Optionally-protected function (feeding) of the WDT * A configurable low major business office agency to reduce go requirements during repose mode * A shape bit for the watchdog scourt that shows the positioning even after a watchdog define 2. . 4 determine author ON determine index number on fix (POR) is provided generally for a system set at power up. The IPOR testament hold the device in fix until all quadruple voltages Vdda, Vcca, Vddd, Vccd, are to datasheet specification. The POR activates automatically at power up and consists of An inexact POR (IPOR) is used to keep the device in define during initial power up of the device until the POR can be delirious A precision POR (PRES) derived from a circumference calibrated for a very precise location of the POR sideslip point. The power on fix clears all the determine spatial relation reads watchdog specifyguard dog fix (WRES) detects fallible code by create a set if the watchdog timepi ece is not open indoors the userspecified time limit. The user mustiness unceasingly set the WRES initialisation code. This was through with(p) to allow the user to dynamically rent whether or not to enable the watchdog timer software program INITIATED reset parcel Initiated readapt (SRES) is a tool that allows a software-driven reset. The RESET_CR2 register forces a device reset when a 1 is write into bit 0. This scope can be made by firmware or with a DMA. The RESET_SR0 5 side bit becomes set on the incident f a software reset. This bit stiff set until unclutter by the user or until a POR reset. extraneous RESET External Reset (XRES_N) is a user-supplied reset that causes conterminous system reset when asserted. XRES_N is open on a give pin on some devices, as well as a divided GPIO pin P12 on all devices. The dual-lane pin is available through a customer-programmed NV bar setting and supports low pin count move that dont take a leak a sanctified XRES_N p in. This path is typically configured during the boot contour immediately after power up. 3. CONCLUSION